A conventional MOS transistor generally includes a semiconductor substrate, such as silicon, having a source, a drain, and a channel positioned between the source and drain. A gate stack composed of a conductive material (a gate conductor), an oxide layer (a gate oxide), and sidewall spacers, is typically located above the channel. The gate oxide is typically located directly above the channel, while the gate conductor, generally comprised of polycrystalline silicon (polysilicon) material, is located above the gate oxide. The sidewall spacers protect the sidewalls of the gate conductor.
Generally, for a given electric field across the channel of a MOS transistor, the amount of current that flows through the channel is directly proportional to the mobility of carriers in the channel. Thus the higher the mobility of the carriers in the channel, the more rapidly the carriers will pass through the channel and the faster a circuit can perform when using high mobility MOS transistors. Additionally, improving the mobility of the carriers in the channel can allow device operation at lower voltages.
A number of techniques can be employed to improve mobility of the carriers in the channel. One technique is to reduce the channel length and/or the thickness of the gate oxide thereby shortening the distances carriers must travel and increasing current drive and switching performance. However, reducing the thickness of the gate oxide results in an increase in gate tunneling current, which in turn degrades the performance of the device by increasing off state leakage. Furthermore, decreasing the thickness of the gate oxide and/or the channel length requires more advanced and expensive lithography technology.
Another technique to increase the mobility of the carriers in the channel of an MOS transistor is to produce a mechanical stress or strain in the channel. A compressive strained channel typically provides hole mobility enhancement, which is particularly beneficial for PMOS devices, whereas a tensile strained channel typically provides electron mobility enhancement, which is particularly beneficial for NMOS devices. Generally, a layer is formed that has a lattice mismatch between the formed layer and underlying substrate and channel. The lattice mismatch then induces strain across a channel region.
One drawback to improving channel mobility via strain is that compressive strain, which generally improves hole mobility for silicon substrate devices, can degrade electron mobility and that tensile strain, which improves electron mobility for silicon substrate based devices, can also degrade hole mobility. As a result, introducing tensile strain can improve performance of NMOS devices but degrade performance of PMOS devices. Similarly, introducing compressive strain can improve performance of PMOS devices but degrade performance of NMOS devices.